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this is information on a product in full production. october 2015 docid028088 rev 3 1/38 VNH7070AS automotive fully integrated h-bridge motor driver datasheet - production data features ? automotive qualified ? output current: 15 a ? 3 v cmos-compatible inputs ? undervoltage shutdown ? overvoltage clamp ? thermal shutdown ? cross-conduction protection ? current and power limitation ? very low standby power consumption ? protection against loss of ground and loss of v cc ? pwm operation up to 20 khz ? cs diagnostic functions ? analog motor current feedback ? output short to ground detection ? thermal shutdown indication ? off-state open-load detection ? output short to v cc detection ? output protected against short to ground and short to v cc ? standby mode ? half bridge operation ? package: ecopack ? description the device is a full bridge motor driver intended for a wide range of automotive applications. the device incorporates a dual monolithic high-side driver and two low-side switches. both switches are designed using stmicroelectronics? well known and proven proprietary vipower ? m0-7 technology that allows to efficiently integrate on the same die a true power mosfet with an intelligent signal/protection circuitry. the three dies are assembled in so-16n package on electrically isolated lead-frames. moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. the input signals in a and in b can directly interface the microcontroller to select the motor direction and the brake condition. a sel0 pin is available to address the information available on the cs to the microcontroller. the cs pin allows to monitor the motor current by delivering a current proportional to the motor current value. the pwm, up to 20 khz, allows to control the speed of the motor in all possible conditions. in all cases, a low level state on the pwm pin turns off both the ls a and ls b switches. type r ds(on) i out v ccmax VNH7070AS 70 m typ ( per leg) 15 a 41 v so-16n gapgcft00648 table 1. device summary package order codes tube tape and reel so-16n ? VNH7070AStr www.st.com
contents VNH7070AS 2/38 docid028088 rev 3 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 off-state open-load detection ? external circuitry dimensioning . . . . . . 23 3.3 immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 24 3.4 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 so16-n thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 package thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.1 thermal characterization in steady state conditions . . . . . . . . . . . . . . . 28 4.2.2 thermal characterization during transients . . . . . . . . . . . . . . . . . . . . . . 29 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 so-16n mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 so-16n packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 so-16n marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
docid028088 rev 3 3/38 VNH7070AS list of tables 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. logic inputs (in a , in b ) (v cc = 7 v up to 28 v; -40 c < t j < 150 c) . . . . . . . . . . . . . . . . . 10 table 8. switching (v cc =13v, r load =3.7 ? ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. protections and diagnostics (v cc = 7 v up to 18 v; -40 c < t j < 150 c). . . . . . . . . . . . . 11 table 10. cs (7 v < v cc < 18 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 11. operative condition - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. on-state fault conditions- truth table fault on leg a (preliminary). . . . . . . . . . . . . . . . . . . . 18 table 13. off-state -truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 14. iso 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . . 24 table 15. thermal model for junction temperature calculation in steady-state conditions\ . . . . . . . . 29 table 16. thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17. so-16n mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 18. reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. so-16n carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 20. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
list of figures VNH7070AS 4/38 docid028088 rev 3 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. t dstkon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. low-side turn-on delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. time to shutdown for the low-side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 9. input reset time for hsd - fault unlatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. input reset time for lsd - fault unlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. off-state diagnostic delay time from rising edge of v out (t d_vol ) . . . . . . . . . . . . . . . . . . 17 figure 12. normal operative conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13. out shorted to ground and short clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. out shorted to vcc and short clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15. application schematic with reverse battery protection connected to vbatt . . . . . . . . . . . . . 22 figure 16. application schematic with reverse battery protection connected to gnd . . . . . . . . . . . . . 22 figure 17. suggested pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18. half-bridge configuration (case a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 19. half-bridge configuration (case b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 20. multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 21. pcb layout (top and bottom): footprint, 2+2+2 cm 2 , 8+8+8 cm 2 . . . . . . . . . . . . . . . . . . . . 27 figure 22. pcb 4 layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 23. chipset configuration configuration in steady state conditions . . . . . . . . . . . . . . . . . . . . . . 28 figure 24. auto and mutual r thj-amb vs. pcb heat-sink area in open box free air condition . . . . . . . . 29 figure 25. hsd thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 26. lsd thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 27. electrical equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 28. so-16n package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 29. so-16n reel 13? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 30. so-16n rcarrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 31. so-16n schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 32. so-16n marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
docid028088 rev 3 5/38 VNH7070AS block diagram and pin description 37 1 block diagram and pin description figure 1. block diagram table 2. block description name description logic control allows the turn-on and the turn-off of the high-side and the low-side switches according to the truth table. undervoltage shuts down the device for battery voltage lower than 4 v. high-side and low-side clamp voltage protect the high-side and the low-side switches from the high voltage on the battery line. high-side and low-side driver drive the gate of the concerned switch to allow a proper r on for the leg of the bridge. current limitation limits the motor current in case of short circuit. high-side and low-side overtemperature protection in case of short-circuit with the increase of the junction temperature, it shuts down the concerned driver to prevent degradation and to protect the die. low-side overload detector detects when low side current exceeds shutdown current and latches off the concerned low side. logic v cc out a in b in a gnd a cs ls a clamp hs a ls a hs a hsa_overtemperature hsb_overtemperature u v current limitation a out b gnd b ls b hs b current driver hs a driver ls b driver hs b driver clamp hs b clamp ls b clamp ls a 1/k 1/k limitation b overload detector b overload detector a power limitation lsb_overtemperature lsa_overtemperature gapgcft01189 open-load off-state a mux sel 0 open-load off-state b fault detection pwm
block diagram and pin description VNH7070AS 6/38 docid028088 rev 3 figure 2. configuration diagram (top view) fault detection signalizes the abnormal behavior of the switch through cs pin. power limitation limits the power dissipation of the high-side driver inside safe range in case of short to ground condition. table 3. pin definitions and functions pin n symbol function 1, 16 gnd a source of low-side switch a 2, 15 out a source of high-side switch a / drain of low-side switch a 3in a clockwise input 4, 5, 12 v cc power supply voltage 6in b counter clockwise input 7, 10 out b source of high-side switch b / drain of low-side switch b 8, 9 gnd b source of low-side switch b 11 pwm voltage controlled input pin with hysteresis, cmos compatible. gates of low-side fets get modulated by the pwm signal during their on phase allowing speed control of the motor 13 cs multiplexed analog sense output pin; it delivers a current proportional to the motor current according to the leg selection. 14 sel 0 active high compatible with 3 v and 5 v cmos outputs pin; in combination with in a , in b , it addresses the currentsense information delivered to the micro according to the operative truth table. table 2. block description (continued) name description 6 2 1 *1' $ 287 $ ,1 9 && 9 && ,1 % 287 % *1' % *1' $ 287 $ &6 9 && 287 % *1' % *$3*&)7 6(/ 3:0 $
docid028088 rev 3 7/38 VNH7070AS electrical specifications 37 2 electrical specifications figure 3. current and voltage conventions 2.1 absolute maximum ratings stressing the device above the rating listed in table 4: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7 $$ 7 065" 7 065# * 065" * 065# * 4&/4& 7 4&/4& * 4 065 " 065 # $4 (/% 7 $$ */ " */ # 4&- 18. * */" * */# * 4&- * 18. * (/% 7 18. 7 4&- 7 */# 7 */" ("1($'5 table 4. absolute maximum ratings symbol parameter value unit v cc supply voltage 38 v -v cc reverse dc supply voltage 0.3 v i max maximum output current (continuous) internally limited a i r reverse output current (continuous) -15 a v ccpk maximum transient supply voltage (iso 16750-2:2010 test b clamped to 40 v; rl = 4 ) 40 v v ccjs maximum jump start voltage for single pulse short circuit protection 28 v i in input current (in a and in b pins) -1 to 10 ma i sel0 sel 0 dc input current -1 to 10 ma i pwm pwm input current -1 to 10 ma i sense cs pin dc output current (v gnd = v cc and v sense <0v 10 ma cs pin dc output current in reverse (v cc < 0 v) -20
electrical specifications VNH7070AS 8/38 docid028088 rev 3 2.2 thermal data v esd electrostatic discharge (human body model: r = 1.5 k ; c = 100 pf) ?in a , in b , pwm ? sel 0 ?cs ?v cc ?output 2 2 2 4 4 kv v esd charge device model (cdm-aec-q100-011) 750 v t c junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 c table 4. absolute maximum ratings (continued) symbol parameter value unit table 5. thermal data symbol parameter max. value unit r thj-pin thermal resistance junction-pin hsd 31 c/w lsd 44 c/w r thj-amb thermal resistance junction-ambient (jedec jesd 51-2) (1) 1. device mounted on two-layers 2s0p pcb. see figure 24 c/w r thj-amb thermal resistance junction-ambient (jedec jesd 51-2) (2) 2. device mounted on four-layers 2s2p pcb. hsd 39.5 c/w lsd 55 c/w
docid028088 rev 3 9/38 VNH7070AS electrical specifications 37 2.3 electrical characteristics values specified in this section are for v cc = 7 v up to 28 v; -40 c < t j < 150 c, unless otherwise specified. table 6. power section symbol parameter test conditions min. typ. max. unit v cc operating supply voltage 428v i s supply current off-state - standby; in a =in b =0; sel 0 = 0; pwm = 0; t j =25c; v cc =13v 1a off-state - standby; in a =in b =0; sel 0 = 0; pwm = 0; v cc =13v; t j =85c 1a off-state - standby; in a =in b =0; sel 0 = 0; pwm = 0; v cc =13v; t j = 125 c 3a off-state (no standby); in a =in b = 0; sel 0 =5v; pwm = 0 24ma on-state: in a or in b =5v; pwm = 0 v or pwm=5 v; sel 0 =x 3.5 6 ma t d_sdby (1) 1. to power on the device from the standby, it is recommended to: ? toggle ina or inb from 0 to 1 first to come out from stby mode ? toggle pwm from 0 to 1 with a delay of 20 s this avoids any over-stress on the device in case of existing short-to-battery. standby mode blanking time v cc =13 v; in a =in b =pmw=0v; v sel0 from 5 v to 0 v 0.2 1 1.8 ms r onhs static high-side resistance i out = 3.5 a; t j = 25c 42 m i out = 3.5 a; t j =-40 to 150c 85 m r onls static low-side resistance i out = 3.5a; t j = 25c 30 m i out = 3.5a; t j = -40c to 150c 60 m v f free-wheeling diode forward voltage i out =-3.5a; t j = 150c 0.7 0.9 v i l(off) off-state output current of one leg in a =in b = 0; pwm = 0; v cc =13v; t j =25c 00.5a in a =in b = 0; pwm = 0; v cc =13v; t j =125c 03a i l(off_h) off-state output current of one leg with other hsd on in a =0; in b = 5 v; pwm = 0; v cc =13v 20 60 a
electrical specifications VNH7070AS 10/38 docid028088 rev 3 table 7. logic inputs (in a , in b ) (v cc =7v up to 28v; -40c docid028088 rev 3 11/38 VNH7070AS electrical specifications 37 table 9. protections and diagnostics (v cc = 7 v up to 18 v; -40 c < t j < 150 c) symbol parameter test conditions min. typ. max. unit v usd undervoltage shutdown 4 v v usdreset undervoltage shutdown reset 5v v usdhyst undervolatge shutdown hysteresis 0.4 v i lim_h high-side current limitation 15 22 30 a i sd_ls shutdown ls current 18 27 36 a t sd_ls time to shutdown for the low-side in a = 5 v; in b =0v; pwm = 5 v (see figure 8 ) 5s v cl_hsd high-side clamp voltage (v cc to out a =0 or out b =0) i out =100ma; t clamp =1ms 38 46 v v cl_lsd low-side clamp voltage (out a =v cc or out b = v cc to gnd) i out =100ma; t clamp =1ms 38 46 v t tsd_hs high-side thermal shutdown temperature in x = 2.1 v 150 175 200 c t tr_hs high-side thermal reset temperature 135 c t hyst_hs high-side thermal hysteresis (t sd_hs -t r_hs ) 7c t tsd_ls low-side thermal shutdown temperature in x = 0 v 150 175 200 c v cl total clamp voltage (v cc to gnd) i out =100ma; t clamp = 1 ms 38 46 52 v v ol off-state open-load voltage detection threshold in a =in b = 0 v; pwm = 0; v sel0 = 5 v for cha; v sel0 = 0 v and within t d_stby for chb 23 4 v i l(off2) off-state output sink current in a =in b =0; v out =v ol ; pwm = 0 v; v sel0 = 5 v for cha; v sel0 = 0 v and within t d_stby for chb -100 -15 a t dstkon off-state diagnostic delay time from falling edge of input (see figure 4 ) in a = 5 v to 0 v; in b =0; v sel0 = 5 v; pwm = 0; i out =0a; v outa =4v 40 140 300 s
electrical specifications VNH7070AS 12/38 docid028088 rev 3 t d_vol off-state diagnostic delay time from rising edge of v out (see figure 11 ) in a =in b = 0 v; pwm = 0; v outx = 0 v to 4 v; v sel0 = 5 v for cha; v sel0 = 0 v and within t d_stby for chb 530s t latch_rst_hs (1) input reset time for high side fault unlatch (see figure 9 ) v inx = 5 v to 0 v; hsdx faulting 31020s t latch_rst_ls (1) input reset time for low side fault unlatch (see figure 10 ) v inx = 0 v to 5 v; lsdx faulting 31020s 1. parameter guaranteed by design and characteriza tion; not subjected to production test. table 10. cs (7 v < v cc <18v) symbol parameter test conditions min. typ. max. unit v sense_cl multisense clamp voltage v cc =18v; i sense =-5ma 11 v cc =18v; i sense =5ma -13 -9 v k 0 i out /i sense i out = 0.05 a; v sense = 0.5 v; t j = -40c to 150c 665 k 1 i out /i sense i out = 0.2 a; v sense = 0.5 v; t j = -40c to 150c 1083 1900 2716 k 2 i out /i sense i out = 3.5 a; v sense = 4 v; t j = -40c to 150c 1315 1540 1779 k 3 i out /i sense i out = 5.5 a; v sense = 4 v; t j = -40c to 150c 1357 1540 1727 dk 0 /k 0 (1)(2) analog sense current drift i out = 0.05 a; v sense = 0.5 v; t j = -40c to 150c -25 25 % dk 1 /k 1 (1)(2) analog sense current drift i out = 0.2 a; v sense = 0.5 v; t j = -40c to 150c -21 21 % dk 2 /k 2 (1)(2) analog sense current drift i out = 3.5 a; v sense =4v; t j = -40c to 150c -5 5 % dk 3 /k 3 (1)(2) analog sense current drift i out = 5.5 a; v sense = 4 v; t j = -40c to 150c -4 4 % v sensesat max analog sense output voltage v cc = 7; r sense = 10 k ? ; v sel0 =5v; i outa = 5.5 a; v ina = 5 v; pwm = 0; t j =150c 5v i sense_sat currentsense saturation current v cc =13v; v ina =5v; v inb =0v; v sense =4v; v sel0 =5v; t j = 150c 4.6 ma i out_sat (2) output saturation current v cc =13v; v sense =4v; v ina =5v; v inb = 0 v; v sel0 =5v; t j =150c 8a table 9. protections and diagnostics (v cc =7v up to 18v; -40c docid028088 rev 3 13/38 VNH7070AS electrical specifications 37 figure 4. t dstkon v out_msd (2) output voltage for multisense shutdown v ina =5v; v inb =0v; v sel0 =5v; r sense =2.7k ? ; i out =3.5a 5v i sense0 cs leakage current i out = 0 a; v sense =0v; in x = 0 v; sel 0 =0; t j = -40c to 150c (standby) 00.5a i out =0a; v sense =0v; in x = 0 v; sel 0 =5v; t j = -40c to 150c (no standby) 00.5a in x = 5 v; pwm = 5 v; i out = 0 a; t j = -40c to 150c 05a v senseh cs output voltage in fault condition v cc =13v; r sense =1k ? ; ? e.g: out a in open-load: v ina =0v; i outa = 0 a; v outa =4v; v sel0 =5v 57v i senseh cs output current in fault condition v cc =13v; v sense =v senseh 72030ma 1. analog sense current drift is devia tion of factor k for a given device over (-40 c to 150 c and 9 v < v cc < 18 v) with respect to its value measured at t j = 25 c, v cc = 13 v. 2. parameter guaranteed by design and characteriza tion; not subjected to production test. table 10. cs (7 v < v cc < 18 v) (continued) symbol parameter test conditions min. typ. max. unit 7 '67.21 9 ,1387 9 287 0xowl6hqvh 9 287 !9 2/ *$3*&)7
electrical specifications VNH7070AS 14/38 docid028088 rev 3 figure 5. definition of the low-side switching times figure 6. definition of the high-side switching times t f pwm t t v outa, b 20% 90% 80% 10% t r t t v outa v ina 90% 10% t d(on) t d(off)
docid028088 rev 3 15/38 VNH7070AS electrical specifications 37 figure 7. low-side turn-on delay time figure 8. time to shutdown for the low-side driver ("1(3* ,1$ 3:0 w furvv 2xw$ ,1% 2xw% w w w w w ("1($'5 , /6' 9 vhqvh , 6'b/6 , rs 9 vhqvh 9 vhqvh+ w 6'b/6 9 vhqvhbqrp
electrical specifications VNH7070AS 16/38 docid028088 rev 3 figure 9. input reset time for hsd - fault unlatch figure 10. input reset time for lsd - fault unlatch *$3*&)7 ,1$ 287$ )dxow+6$ )dxowuhprylqj 5hvhw3xovh 0xowl6hqvh )dxowfohdqlqj 9 pxowlbvhqvh+ 9 vhqvhbqrp 7odwfkb567b+6' *$3*&)7 ,1$ 287$ )dxow/6$ )dxowuhprylqj 0xowlvhqvh )dxowfohdqlqj 9 pxowlbvhqvh+ 5hvhw3xovh 2xw$6kruwwr9&& wfurvv 7b/dfkwb567b/6'
docid028088 rev 3 17/38 VNH7070AS electrical specifications 37 figure 11. off-state diagnostic delay time from rising edge of v out (t d_vol ) *$3*&)7 ,1$ 287$ &6 9 vhqvh+ w 'b92/ )dxow9 287 !9 2/
electrical specifications VNH7070AS 18/38 docid028088 rev 3 table 11. operative condition - truth table pin status hsds and ldss status in a in b sel 0 pwm cs hsda lsda hsdb lsdb 11 1 x current monitoring hsda on off on off 0 current monitoring hsdb 101 1 current monitoring hsda on off off on 0onoffoffoff 100 1 hi-z on off off on 0onoffoffoff 011 1 hi-z off on on off 0offoffonoff 010 1 current monitoring hsdb off on on off 0offoffonoff 00 1 1hi-zoffonoffon 0 00 1 0x (1) 1. refer to table 13: off-state -truth table off off off off 0 (2) 2. for in a =in b =sel 0 = pwm = 0, the device enters in standby after t d_sdby off off off off table 12. on-state fault conditions- tr uth table fault on leg a (preliminary) in a in b sel 0 pwm out a out b cs fault description on state diagnostic 101 x l l v senseh out a short to gnd 100 1 h h v senseh out b short to v cc 011 1 h h v senseh out a short to v cc 010 x x l v senseh out b short to gnd
docid028088 rev 3 19/38 VNH7070AS electrical specifications 37 table 13. off-state -truth table in a in b sel 0 pwm out a out b cs description off-state diagnostic 00 1 0 v outa >v ol xv senseh case 1. out a shorted to v cc if no pull-up is applied case 2. no open-load in full bridge configuration with an external pull-up on out b case 3. open-load in half bridge configuration with an external pull-up on out a (motor connected between out a and ground) v outa v ol v senseh case 1. out b shorted to v cc if no pull-up is applied case 2. no open-load in full bridge configuration with external pull-up on out a case 3. open-load in half bridge configuration with external pull-up on out b (motor connected between out b and ground) xv outb electrical specifications VNH7070AS 20/38 docid028088 rev 3 2.4 waveforms figure 12. normal operative conditions figure 13. out shorted to ground and short clearing 9,1$ 9,1% 93:0 96(/ 9287$ 9287% ,/rdg 9vhqvh ("1($'5 s /e s /e s wtd s ^> s khd s khd s ^e^ / >k s ^v?, s ?v?zv}u / >}zv}u z??wo? z??wo? k?^z}???}'v k?^z}???}'v &o?zu}]vp &o?zu}]vp ("1($'5 0vuy4ipsufe5p(oe'bvmu$mfbsjoh
docid028088 rev 3 21/38 VNH7070AS electrical specifications 37 figure 14. out shorted to vcc and short clearing s /e s /e s wtd s ^> s khd s khd s ^e^ / >k z??wo? z??wo? k?^z}???}s k?^z}???}s &o?zu}]vp &o?zu}]vp s ^v?, / >}zv}u ("1($'5 0vuy4ipsufe5p7dd'bvmu$mfbsjoh
application information VNH7070AS 22/38 docid028088 rev 3 3 application information here following there is the typical application schematic suggested for a proper operation of the device in dc or pwm conditions. figure 15. application schematic with reverse battery protection connected to vbatt figure 16. application schematic with reve rse battery protection connected to gnd ("1($'5 +6$ 287% +6% /6% /6$ 0 *1' 287$ ,1$ 3:0 6(/ &6 9ff ?& ,1% . . 5hj 9 q 5vhqvh *1' 9%dww & ?) 30rvihw . q) 5sxoobxs ([whuqdo sxooxs vzlwfk 2shqordglqrii vwdwhghwhfwlrq flufxlwu\ =' 9 . . . ("1($'5 +6$ 287% +6% /6% /6$ 0 *1' 287$ ,1$ 3:0 6(/ &6 9ff ?& 9ff 10rvihw . ,1% . 5hj9 q 5vhqvh *1' 5sxoobxs ([whuqdo sxooxs vzlwfk 2shqordglqrii vwdwhghwhfwlrq flufxlwu\ q) ']!9 & ?) q) . . . .
docid028088 rev 3 23/38 VNH7070AS application information 37 figure 17. suggested pcb layout note: pcb layout recommendation: optimized connection (short) between drain lsd and source hsd optimized gnda and gndb connection (symmetric connection) 3.1 reverse battery protection three possible solutions can be considered: ? a schottky diode d connected to v cc pin ? an n-channel mosfet connected to the gnd pin ? a p-channel mosfet connected to the v cc pin in case the reverse battery protection is not present, the device sustains no more than -15 a because of the two body diodes of the power mosfets. additionally, in reverse battery condition the i/os of the device is pulled down to the v cc line (approximately -1.5 v). series resistor must be inserted to limit the current sunk from the microcontroller i/os. if i rmax is the maximum target reverse current through microcontroller i/os, series resistor is: 3.2 off-state open-load detection ? external circuitry dimensioning the detection of an open-load in off state requires an external circuitry to be connected between output and v batt . for the detection it is necessary to put one network on each leg in case of half bridge operation or one network on one of the output in case of full bridge (see table 13: off-state -truth table ). the external circuitry is made up by an external pull-up resistor r pull_up connecting the output to a positive supply voltage v pu (v batt ). r v ios v cc ? i rmax ------------------------------ =
application information VNH7070AS 24/38 docid028088 rev 3 it is preferable to switch-off v pu by using an external pull_up switch to reduce the overall standby current during he module standby mode. r pull_up must be dimensioned to ensure that in normal operative conditions v out > v olmax . to satisfy this condition the r pull_up must be selected according to: ? if the device is used in half bridge configuration, the equation is: ? if the device is used in h-bridge configuration, the equation is: 3.3 immunity against transient electrical disturbances the immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the v cc pin, is tested in accordance with iso7637-2:2011 (e) and iso 16750-2:2010. the related function performance status classification is shown in tab le 14 . test pulses are applied directly to dut (device under test) both in on and off-state and in accordance to iso 7637-2:2011(e), chapter 4. the dut is intended as the present device only, without components and accessed through v cc and gnd terminals. status ii is defined in iso 7637-1 function performance status classification (fpsc) as follows: ?the function does not perform as designed during the test but returns automatically to normal operation after the test?. r pull_up v battmin v olmax ? i l(off2)min[@volmax] ------------------------------------------------------- - < ? 2i l(off2)min[@volmax] ------------------------------------------------------------- - < table 14. iso 7637-2 - electrical transient conduction along supply line test pulse 2011(e) test pulse severity level with status ii functional performance status minimum number of pulses or test time burst cycle / pulse repetition time pulse duration and pulse generator internal impedance level u s (1) 1. u s is the peak amplitude as defined for each test pulse in iso 7637-2:2011(e), chapter 5.6. min max 1 iii -112 v 500 pulses 0,5 s 2ms, 10 2a iii +55 v 500 pulses 0,2 s 5 s 50s, 2 3a iv -220 v 1h 90 ms 100 ms 0.1s, 50 3b iv +150 v 1h 90 ms 100 ms 0.1s, 50 4 (2) iv -7 v 1 pulse 100ms, 0.0 1 load dump according to iso 16750-2:2010 te st b (3) 40 v 5 pulse 1 min 400 ms, 2
docid028088 rev 3 25/38 VNH7070AS application information 37 3.4 device configurations figure 18. half-bridge configuration (case a) note: the VNH7070AS can be used in half bridge configuration as the two legs can be independently driven. the sel0 pin can be used to address the diagnostic on the cs according to the operative truth table. figure 19. half-bridge configuration (case b) note: the VNH7070AS can be used in applications where an half-bridge with a resistance of 50 m ? per leg is needed. 2. test pulse from iso 7637-2:2004(e). 3. with 40 v external suppressor referred to ground (-40c < t j < 150c). 0 0 ,1$ 2xw$ 3:0 ,1% 6(/ 2xw% *1' *1' *1' 9ff &6 ("1($'5 0 ,1$ 2xw$ 3:0 6(/ &6 2xw% ,1$ 3:0 6(/ &6 2xw$ 2xw% ,1% ,1% *1' *1' 9ff ("1($'5
application information VNH7070AS 26/38 docid028088 rev 3 figure 20. multi-motors configuration note: the VNH7070AS can easily be designed in multi motor driving configuration in the applications where only one motor at a time must be activated. the sel0 pin can be used to read the diagnostic on the cs according to the operative truth table. ("1($'5 0 0 0 ,1$ 2xw$ 3:0 6(/ &6 2xw% ,1$ 3:0 6(/ &6 2xw$ 2xw% ,1% ,1% 9ff *1' *1'
docid028088 rev 3 27/38 VNH7070AS package and pcb thermal data 37 4 package and pcb thermal data 4.1 so16-n thermal data figure 21. pcb layout (top and bottom): footprint, 2+2+2 cm 2 , 8+8+8 cm 2
package and pcb thermal data VNH7070AS 28/38 docid028088 rev 3 figure 22. pcb 4 layer note: board finish thickness 1.6 mm +/- 10%; board double layer and four layers; board dimension 77x86 mm; board material fr4; cu thickness 0.070mm (outer layers); cu thickness 0.035mm (inner layers); thermal vias separation 1.2 mm; thermal via diameter 0.3 mm +/- 0.08 mm; cu thickness on vias 0.025 mm. 4.2 package thermal data 4.2.1 thermal characterization in steady state conditions figure 23. chipset configuration configuration in steady state conditions $ijq 3 ui# $ijq 3 ui" $ijq 3 ui$ 3 ui"# 3 ui"$ 3 ui#$ ("1($'5
docid028088 rev 3 29/38 VNH7070AS package and pcb thermal data 37 figure 24. auto and mutual r thj-amb vs. pcb heat-sink area in open box free air condition 4.2.2 thermal characterization during transients t hs = pd hs ? z hs + z hsls ? (pd lsa + pd lsb ) + t amb t lsa = pd lsa ? z ls + pd hs ? z hsls + pd lsb ? z lsls + t amb t lsb = pd lsb ? z ls + pd hs ? z hsls + pd lsa ? z lsls + t amb table 15. thermal model for junction temperature calculation in steady-state conditions\ chip 1 chip 2 chip 3 tjchip1 tjchip2 tjchip3 on off on p dchip1 ? r tha + p dchip3 ? r thac + t amb p dchip1 ? r thab + p dchip3 ? r thbc + t amb p dchip1 ? r thac + p dchip3 ? r thc + t amb on on off p dchip1 ? r tha + p dchip2 ? r thab + t amb p dchip1 ? r thab + p dchip2 ? r thb + t amb p dchip1 ? r thac + p dchip2 ? r thbc + t amb on off off p dchip1 ? r tha + t amb p dchip1 ? r thab + t amb p dchip1 ? r thac + t amb on on on p dchip1 ? r tha + (p dchip2 + p dchip3 ) ? r thab + t amb p dchip2 ? r thb + p dchip1 ? r thab + p dchip3 ? r thbc + t amb p dchip1 ? r thab + p dchip2 ? r thbc + p dchip3 ? r thc + t amb ("1($'5 ?&: fp ri&x$uhduhihuwr3&%/d\huod\rxw 5wk$ 5wk% 5wk& 5wk$% 5wk$& 5wk%&
package and pcb thermal data VNH7070AS 30/38 docid028088 rev 3 figure 25. hsd thermal impedance junction ambient single pulse figure 26. lsd thermal impedance junction ambient single pulse ("1($'5 ?&: wlphvhf =7++6'#fxduhd +6'irrwsulqw +6'fpa&x +6'fpa&x +6'/d\hu +v/v'irrwsulqw +v/v'fpa&x +v/v'fpa&x +v/v'/d\hu = kv = kvov ("1($'5 ?&: wlphvhf =7+/6'#fxduhd /6'irrwsulqw /6'fpa&x /6'fpa&x /6'/d\hu /v/v'irrwsulqw /v/v'fpa&x /v/v'fpa&x /v/v'/d\hu = ov = ovov
docid028088 rev 3 31/38 VNH7070AS package and pcb thermal data 37 figure 27. electrical equivalent model table 16. thermal parameters area/island (cm 2 )fp 2 8 4l r1 (c/w) 2.4 2.4 2.4 2.4 r2 (c/w) 12 12 12 12 r3 (c/w) 31 26 26 30 r4 (c/w) 42 12 12 8 r5 (c/w) 86 46 31 16 r6 (c/w) 2.4 2.4 2.4 2.4 r7 (c/w)4444 r8 (c/w) 11 11 11 11 r9 (c/w) 32 32 32 32 r10 (c/w) 68 52 48 22 r11 (c/w) 75 80 60 26 r12 (c/w)4444 r13 (c/w) 11 11 11 11 r14 (c/w) 32 32 32 32 r15 (c/w) 68 52 48 10 r16 (c/w) 75 80 60 26 r17 (c/w) 120 100 100 100 r18 (c/w) 120 100 100 100 r19 (c/w) 180 170 170 170 r20 (c/w) 180 170 170 170
package and pcb thermal data VNH7070AS 32/38 docid028088 rev 3 c1 (ws/c) 0.0008 0.0008 0.0008 0.0008 c2 (ws/c) 0.015 0.015 0.015 0.015 c3 (ws/c) 0.08 0.08 0.08 0.08 c4 (ws/c) 0.2 0.5 1 1 c5 (ws/c) 1.5 2 6 12 c6 (ws/c) 0.0008 0.0008 0.0008 0.0008 c7 (ws/c) 0.001 0.001 0.001 0.001 c8 (ws/c) 0.015 0.015 0.015 0.015 c9 (ws/c) 0.04 0.04 0.04 0.04 c10 (ws/c) 0.08 0.1 0.1 0.2 c11 (ws/c) 1 2.5 3 6 c12 (ws/c) 0.001 0.001 0.001 0.001 c13 (ws/c) 0.015 0.015 0.015 0.015 c14 (ws/c) 0.04 0.04 0.04 0.04 c15 (ws/c) 0.08 0.1 0.1 0.2 c16 (ws/c) 1 2.5 3 6 table 16. thermal parameters (continued) area/island (cm 2 )fp 2 8 4l
docid028088 rev 3 33/38 VNH7070AS package and packing information 37 5 package and packing information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 5.1 so-16n mechanical data figure 28. so-16n package dimensions ("1($'5
package and packing information VNH7070AS 34/38 docid028088 rev 3 5.2 so-16n packing information figure 29. so-16n reel 13? table 17. so-16n mechanical data symbol millimeters min. typ. max. a 1.75 a1 0.10 0.25 a2 1.25 b0.31 0.51 c0.17 0.25 d 9.80 9.90 10.00 e 5.80 6.00 6.20 e1 3.80 3.90 4.00 e1.27 h0.25 0.50 l0.40 1.27 k0 8 ccc 0.1 "ddftt)pmfbu 4mpu-pdbujpo nnnjo
*gqsftfou ubqftmpujodpsf gpsubqftubsu nnnjoxjeuiy nnnjoefqui 5"1($'5 $ / 8 8 % " #
docid028088 rev 3 35/38 VNH7070AS package and packing information 37 figure 30. so-16n rcarrier tape table 18. reel dimensions description value (1) 1. all dimensions are in mm. base quantity 2500 bulk quantity 2500 a (max) 330 b (min) 1.5 c (+0.5, -0.2) 13 d (min) 20.2 n100 w1 (+2 /-0) 16.4 w2 (max) 22.4 table 19. so-16n carrier tape dimensions description value a 0 6.55 0.1 b 0 10.38 0.1 k 0 2.10 0.1 k 1 1.80 0.1 f 7.50 0.1 ("1($'5
package and packing information VNH7070AS 36/38 docid028088 rev 3 figure 31. so-16n schematic drawing of leader and trailer tape 5.3 so-16n marking information figure 32. so-16n marking information note: engineering samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. these samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by st. st is not liable for any customer usage in production and/or in reliability qualification trials. commercial samples: fully qualified parts from st standard production with no usage restrictions. p 1 8.00 0.1 w 16.00 0.3 table 19. so-16n carrier tape dimensions (continued) description value ("1($'5 40/5017*&8 opujotdbmf
4qfdjbmgvodujpoejhju &4&ohjoffsjohtbnqmf cmbol$pnnfsdjbmtbnqmf .bsljohbsfb
docid028088 rev 3 37/38 VNH7070AS revision history 37 6 revision history table 20. document revision history date revision changes 16-jul-2015 1 initial release. 06-oct-2015 2 table 4: absolute maximum ratings : ?-i gnd : removed row updated table 5: thermal data table 6: power section : ?v f : updated parameter table 8: switching (v cc =13v, r load =3.7 ? ) : ?t cross : updated value table 9: protections and diagnostics (v cc = 7 v up to 18 v; -40 c < t j < 150 c) : ?t dstkon : updated value table 10: cs (7 v < v cc <18v) : ?k 1 , k 2 , k 3 , i sense_sat , i out_sat : updated values updated figure 9: input reset time for hsd - fault unlatch and figure 10: input reset time for lsd - fault unlatch added section 2.4: waveforms and updated chapter 3: application information 15-oct-2015 3 table 9: protections and diagnostics (v cc = 7 v up to 18 v; -40 c < t j < 150 c) : ?v cl : updated test conditions
VNH7070AS 38/38 docid028088 rev 3 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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